1. Field of the Invention
The present invention relates to a digital memory device and, more specifically, to an integrated cache random access memory (RAM).
2. Art Background
Digital systems that include a central processing unit (CPU) that frequently access data in a random access main memory often include a cache memory to provide faster access to data. The cache memory is located relatively close to the CPU and typically implements high speed logic circuitry. The cache memory stores a subset of the data that resides in the main memory. When the CPU attempts to read data from the main memory, the cache memory is checked to determine whether the accessed data resides in the cache memory. If so, the data is read from the cache memory which is faster than accessing main memory.
The cache memory contains data that is most likely to be accessed by the CPU. Typically, this data is located at an address adjoining the address of data that is currently read by the CPU. Thus, if the CPU reads data that does not currently reside within the cache memory, the data adjoining the currently accessed data is written from the main memory to the cache memory to update the cache memory. In this manner, the cache memory contains the data that the CPU will most likely access, which in turn increases the performance of the computer system since the cache memory access is faster than an access from main memory.
Prior art cache memories are typically fabricated on three different integrated circuits. By employing three integrated circuits instead of one, the size of the cache memory is increased. Further, three integrated circuits consume more power than a single integrated circuit.
The present invention provides a cache memory with a novel architecture that may be implemented on a single integrated circuit chip.